IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 190

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

BFM Procedures and Functions
5–40
PCI Express Compiler User Guide
Syntax
Arguments
Table 5–24. ebfm_cfgrd_wait Procedure
ebfm_cfgrd_wait(bus_num, dev_num, fnc_num, regb_ad, regb_ln,
lcladdr, compl_status)
bus_num
dev_num
fnc_num
regb_ad
regb_ln
lcladdr
compl_status
ebfm_cfgrd_wait Procedure
The ebfm_cfgrd_wait procedure reads up to four bytes of data from
the specified configuration register and stores the data in BFM shared
memory. This procedure waits until the read completion has been
returned.
PCI Express bus number of the target device
PCI Express device number of the target device
Function number in the target device to be accessed
Byte-specific address of the register to be written.
Length, in bytes, of the data read. Maximum length is four bytes. The
regb_ln
BFM shared memory address of where the read data should be placed
Completion status for the configuration transaction.
In VHDL, this argument is a
by the procedure on return.
In Verilog HDL, this argument is reg [2:0].
In both languages, this is the completion status as specified in the PCI
Express specification:
PCI Express Compiler Version 6.1
compl_status
000
001
010
100
and the
regb_ad
Definition
SC —Successful completion
UR —Unsupported Request
CRS —Configuration Request Retry Status
CA
std_logic_vector
arguments cannot cross a DWORD boundary.
—Completer Abort
(2 downto 0) and is set
Altera Corporation
December 2006