IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 128

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Signals
3–90
PCI Express Compiler User Guide
cal_blk_clk
reconfig_clk
reconfig_togxb
reconfig_fromgxb
Table 3–38. alt2gxb Support Signals
Signal
I
I
I
O
I/O
Physical Layer Interface Signals
This section describes signals for the three possible types of physical
interfaces (1-bit, 20-bit, or PIPE). Refer to
diagram of all of the PCI Express MegaCore function signals.
The
clock (
have their
only one calibration block per device. This input should be connected to a clock
operating as recommended by the Stratix II GX Device Handbook.
The
ALT2GXB dynamic reconfiguration is not supported for PCI Express. Therefore,
this signal usually can be tied low in your design. This signal is provided for cases
in which the PCI Express instance shares a Stratix II GX transceiver quad with
another protocol that supports dynamic reconfiguration. In these cases, this signal
must be connected as described in the Stratix II GX Device Handbook.
The
data input. ALT2GXB dynamic reconfiguration is not supported for PCI Express.
Therefore, this bus usually can be tied '010' in your design. This bus is provided for
cases in which the PCI Express instance shares a Stratix II GX transceiver quad
with another protocol that supports dynamic reconfiguration. In these cases, this
signal must be connected as described in the Stratix II GX Device Handbook.
The
data output. ALT2GXB dynamic reconfiguration is not supported for PCI Express.
Therefore, this output signal can be left unconnected in your design. This signal is
provided for cases in which the PCI Express instance shares a Stratix II GX
transceiver quad with another protocol that supports dynamic reconfiguration. In
these cases, this signal must be connected as described in the Stratix II GX Device
Handbook.
PCI Express Compiler Version 6.1
cal_blk_clk
reconfig_togxb[2:0]
reconfig_fromgxb
reconfig_clk
cal_blk_clk
cal_blk_clk
input signal is connected to the ALT2GXB calibration block
) input. All instances of ALT2GXB in the same device must
input signal is the ALT2GXB dynamic reconfiguration clock.
inputs connected to the same signal because there is
output signal is the ALT2GXB dynamic reconfiguration
input bus is the ALT2GXB dynamic reconfiguration
Description
Figure 3–12 on page 3–44
Altera Corporation
December 2006
for a