IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 219

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
December 2006
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Table A–1. Configuration Signals for x1 and x4 MegaCore Functions (Part 3 of 6)
Signal
Power Management:
Endpoint L1 Acceptable
Latency
Fixed to 0
Fixed to 0
Calculated from the
number of lanes
Power Management:
Enable L1 ASPM
Power Management: L1
Exit Latency Common
Clock
Power Management: L1
Exit Latency Separate
Clock
Fixed to 0
Capabilities: Tags
Supported
Fixed to 0
Power Management:
N_FTS Separate
Power Management:
N_FTS Common
Capabilities: Link Port
Number
Capabilities: Implement
ECRC Check
Capabilities: Implement
ECRC Generation
Fixed to 0
Capabilities: MSI
Messages Requested
Capabilities: MSI Message
64 bit Capable
Capabilities: MSI Per
Vector Masking
Value or Wizard
Page/Label
PCI Express Compiler Version 6.1
Device capabilities register: endpoint L1 acceptable
latency. 0 =< 1 μs, 1 = 1 - 2 μs, 2 = 2 - 4 μs, 3 = 4 - 8 μs,
4 = 8 - 16 μs, 5 = 16 - 32 μs, 6 = 32 - 64 μs, 7 => 64 μs.
Reserved.
Reserved.
Link capabilities register: maximum link width. 1 = x1,
4 = x4, others = reserved.
Link capabilities register: active state power
management support. 01 = L0s, 11 = L1 and L0s.
Link capabilities register: L1 exit latency - separate
clock. 0 =< 1 μs, 1 = 1 - 2 μs, 2 = 2 - 4 μs, 3 = 4 - 8 μs,
4 = 8 - 16 μs, 5 = 16 - 32 μs, 6 = 32 - 64 μs, 7 =>64 μs.
Link capabilities register: L1 exit latency - common
clock. 0 =< 1 μs, 1 = 1 - 2 μs, 2 = 2 - 4 μs, 3 = 4 - 8 μs,
4 = 8 - 16 μs, 5 = 16 - 32 μs, 6 = 32 - 64 μs, 7 => 64 μs.
Reserved.
Number of tags supported for non-posted requests
transmitted.
Reserved.
Number of fast training sequences needed in separate
clock mode (N_FTS).
Number of fast training sequences needed in common
clock mode (N_FTS).
Link capabilities register: port number.
Advanced error capabilities register: ECRC check
enable.
Advanced error capabilities register: ECRC generation
enable.
Reserved.
MSI capability message control register: multiple
message capable request field. 0 = 1 message, 1 = 2
messages, 2 = 4 messages, 3 = 8 messages, 4 = 16
messages, 5 = 32 messages.
MSI capability message control register: 64-bit
capable. 0 = 32b, 1 = 64b or 32b.
Per-bit vector masking (RO field).
PCI Express Compiler User Guide
Description
A–3