IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 126

IP CORE Renewal Of IP-PCIE/8

IPR-PCIE/8

Manufacturer Part Number
IPR-PCIE/8
Description
IP CORE Renewal Of IP-PCIE/8
Manufacturer
Altera
Type
MegaCorer
Datasheets

Specifications of IPR-PCIE/8

Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x8 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
Signals
3–88
PCI Express Compiler User Guide
cpl_err[2:0]
cpl_pending
Table 3–36. Completion Interface Signals
Signal
I
I
I/O
Completion error. This signal reports completion errors to the configuration space. The
three types of errors that the application layer must report are:
Completion pending. The application layer must assert this signal when a master block
is waiting for completion, i.e., a transaction is pending. If this signal is asserted and low
power mode is requested, the MegaCore function waits for deassertion of this signal
before transitioning into low-power state.
Completion time out error:
master-like interface has performed a non-posted request that never receives a
corresponding completion transaction after the 50 ms time-out period. The
MegaCore function automatically generates an error message that is sent to the
root complex.
Completer abort error:
block cannot process a non-posted request. In this case, the target block generates
and sends a completion packet with completer abort (CA) status to the requestor
and then asserts this error signal to the MegaCore function. The block automatically
generates the error message and sends it to the root complex.
Unexpected completion error:
master block detects an unexpected completion transaction, i.e., no completion
resource is waiting for a specific packet.
Completion Interface Signals
Table 3–36
PCI Express Compiler Version 6.1
shows the function’s completion interface signals.
cpl_err[1]
cpl_err[0]
cpl_err[2]
Description
: This signal must be asserted when a target
: This signal must be asserted when a
: This signal must be asserted when a
Altera Corporation
December 2006

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