IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 183

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench & Example Designs
BFM Procedures
and Functions
Altera Corporation
December 2006
■
■
These routines take as parameters a BAR number to access the memory
space and the BFM shared memory address of the bar_table data
structure that was set up by the ebfm_cfg_rp_ep procedure (see
“Configuration of Root Port and Endpoint” on page
parameters simplifies the BFM test driver routines that access an offset
from a specific BAR and eliminates calculating the addresses assigned to
the specified BAR.
The root port BFM does not support accesses to endpoint I/O space
BARs.
For further details on these procedure calls, see the section
Read/Write Request Procedures” on page
This section documents the interface to all of the BFM procedures,
functions, and tasks that the BFM driver uses to drive endpoint
application testing.
1
This section describes both VHDL procedures and functions and Verilog
HDL functions and tasks where applicable. Although most VHDL
procedure are implemented as Verilog HDL tasks, some VHDL
procedures are implemented as Verilog functions rather than Verilog
HDL tasks to allow these functions to be called by other Verilog HDL
functions. Unless explicitly specified otherwise, all procedures in the
following sections also are implemented as Verilog HDL tasks.
1
ebfm_barrd_wait — reads data from an offset of a specific
endpoint BAR and stores it in BFM shared memory. This procedure
blocks waiting for the completion data to be returned before
returning control to the caller.
ebfm_barrd_nowt — reads data from an offset of a specific
endpoint BAR and stores it in the BFM shared memory. This
procedure returns as soon as the request has been passed to the VC
interface module for transmission. This allows subsequent reads to
be issued in the interim.
PCI Express Compiler Version 6.1
The last subsection describes procedures that are specific to the
chaining DMA example design
The Verilog HDL user can see some underlying procedures and
functions that are called by other procedures that normally are
hidden in the VHDL package. These undocumented procedures
are not intended to be called by the user.
PCI Express Compiler User Guide
5–42.
5–30). Using these
“BFM
5–33