IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 203

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench & Example Designs
Altera Corporation
December 2006
EBFM_MSG_ERROR_FATAL_TB_ERR
Syntax
Argument
Return
Table 5–35. Log Messages Using VHDL Constants - Subtype NATURAL (Part 2 of 2)
Table 5–36. ebfm_display Procedure
Constant (Message Type)
VHDL: ebfm_display(msg_type, message)
Verilog HDL: dummy_return:=ebfm_display(msg_type, message);
msg_type
message
always 0
PCI Express Compiler Version 6.1
Used for BFM test
driver or root port BFM
fatal errors. Specifies
an error that stops
simulation because the
error left the testbench
in a state where further
simulation is not
possible. Use this error
message for errors that
occur due to a problem
in the BFM test driver
module or the root port
BFM, and is not caused
by the endpoint
application layer being
tested.
Message type for the message. Should be one of the constants
defined in
In VHDL, this argument is VHDL type string and contains the
message text to be displayed.
In Verilog HDL, the message string is limited to a maximum of 100
characters. Also, because Verilog HDL does not allow variable
length string This routine strips off leading characters of 8’h00
before displaying the message.
This applies only to the Verilog HDL routine.
Description
Table 5–35 on page
Number
N/A
Mask
Bit
5–52.
PCI Express Compiler User Guide
Y
Cannot
suppress
Display
Default
by
Y
Cannot
suppress
Simulation
Stops by
Default
FATAL:
Message
Prefix
5–53