IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 136

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

External PHY Support
Figure 4–2. 16-bit SDR Mode with a Source Synchronous TxClk
4–4
PCI Express Compiler User Guide
clk125_out
ck125_in
refclk
External connection in user logic
rxdata
txdata
txclk (~refclk)
■
This is the only external PHY mode that does not require a PLL. However,
if the slow tlp_clk feature is used with this PIPE interface mode, then a
PLL is required to create the slow tlp_clk. In the case of the slow
tlp_clk, the circuit is similar to the one shown previously in
the 16-bit SDR, but with TxClk output added.
refclk also clocks a DDR register that is used to create a center
aligned TxClk.
125Mhz 16-bit SDR Mode with txclk
PCI Express Compiler Version 6.1
Q 1
Q
Q 4
Q
Q 1
Q 4
A
D
1
4
tlp_clk @ 125Mhz
DDIO
ENB
ENB
ENB
ENB
Q 1
Q 4
D
D
D
A
A
A
PCIe IP MegaCore
clk125_in
refclk
tlp_clk
clk125_out
Altera Corporation
December 2006
Figure
4–1,