IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 172

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Test Driver Modules
5–22
PCI Express Compiler User Guide
6.
7.
e.
f.
If a suitable BAR was found for the DMA channel test, the BFM
attempts the legacy interrupt test:
a.
b.
c.
d.
e.
If a suitable BAR was found for the legacy interrupt test, the BFM
attempts the MSI interrupt test:
a.
b.
c.
d.
PCI Express Compiler Version 6.1
Waits for the DMA channel to finish by checking the DMA
channel in-progress bit in the control register space until it is
clear. This is done by a loop around the call to the
ebfm_barrd_wait procedure in altpcietb_bfm_rdwr.
Checks the data transferred back from the master memory by
the DMA channel to ensure the data is the same as the data that
was initially written. This is done by a call to the
shmem_chk_ok procedure in altpcietb_bfm_shmem.
Checks to see if the endpoint supports legacy interrupts. If so
the test proceeds, otherwise the test finishes.
Checks the MSI message control register to see if the MSI is
disabled. If MSI is enable, then the test disables MSI.
Sets a watchdog timer and writes to the endpoint register to
trigger a legacy interrupt.
Waits to receive a legacy interrupt or until the watchdog timer
expires.
Reports the results of the test, restores the value of the MSI
message control register, and clears the interrupt bit in the EP.
Checks the MSI capabilities register to see how many MSI
registers are supported.
Initializes the MSI capabilities structure with the target MSI
address, data, and number of messages granted to the EP.
Checks each MSI number by triggering the MSI in the endpoint,
then polling the BFM shared memory for an interrupt from the
EP. The test then loops through all MSIs that the EP supports.
The test next checks that each MSI is received before the
watchdog timer expires, and that the MSI data received is
correct.
Restores the MSI control register to the pre-test state, and
reports the results of the test.
Altera Corporation
December 2006