IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 179

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench & Example Designs
Altera Corporation
December 2006
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All of the files for the BFM are generated by the MegaWizard interface in
the testbench/<variation name> directory.
BFM Memory Map
The BFM shared memory is configured to be 2MB in size. The BFM shared
memory is mapped into the first 2MB of I/O space and also the first 2MB
of memory space. When the endpoint application generates an I/O or
memory transaction in this range, the BFM reads or writes the shared
memory.
Configuration Space Bus and Device Numbering
The root port interface is assigned to be device number 0 on internal bus
number 0.
The endpoint can be assigned to be any device number on any bus
number (greater than 0) through the call to procedure ebfm_cfg_rp_ep.
The specified bus number is assigned to be the secondary bus in the root
port configuration space.
modules and handles them at an RTL level to interface to the PCI
Express link. You do not need to access this module directly to adapt
the testbench to test your endpoint application.
VC0:3 Interfaces (altpcietb_bfm_vc_intf) — These interface
modules handle the VC-specific interfaces on the root port interface
model. They take requests from the BFM request interface and
generate the required PCI Express transactions. They handle
completions received from the PCI Express link and notify the BFM
request interface when requests are complete. Additionally, they
handle any requests received from the PCI Express link, and store or
fetch data from the shared memory before generating the required
completions.
Root port interface model (altpcietb_bfm_rpvar_64b_x8_pipen1b)
— This is an IP functional simulation model of a version of the
MegaCore function specially modified to support root port
operation. It’s application layer interface is very similar to the
application layer interface of the MegaCore function used for
endpoint mode.
PCI Express Compiler Version 6.1
PCI Express Compiler User Guide
5–29