IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 115

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Figure 3–33. Stratix II GX PHY x1 & x4 100 MHz Reference Clock
Altera Corporation
December 2006
Stratix II GX PHY X8 100 MHz Reference Clock
When the Stratix II GX PHY is used in a x8 configuration the 100 MHz
clock is connected directly to the ALT2GXB transceiver. The clk250_out is
driven by the output of the ALT2GXB transceiver.
The clk250_out must be connected back to the clk250_in input, possibly
through any distribution circuit needed in the specific application. All of
the interfaces of the function, including the user application interface and
the PIPE interface are synchronous to the clk250_in input. See
on page 3–78
Clock Source
100-MHz
PCI Express Compiler Version 6.1
User and PIPE
interface signals
are synchronous
to clk125_in
for this clocking configuration.
refclk
clk125_in
altpcie_64b_x4_pipen1b: Stratix II GX (or x1)
pll_inclk
clk
ALTGXB Transceiver
MegaCore Function
All Logic in
PCI Express Compiler User Guide
coreclkout
Figure 3–34
clk125_out
3–77