IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 130

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Signals
3–92
PCI Express Compiler User Guide
txdatan_extn[15:0]
txdatakn_ext[1:0]
(1)
txdetectrxn_ext
(1)
txelecidlen_ext
(1)
txcompln_ext
(1)
rxpolarityn_ext
(1)
powerdownn_ext[1:0]
(1)
rxdatan_ext[15:0]
(1)
rxdatakn_ext[1:0]
(1)
rxvalidn_ext
(1)
phystatusn_ext
(1)
rxelecidlen_ext
(1)
rxstatusn_ext[2:0]
(1)
Table 3–40. PIPE Interface Signals (Part 1 of 2)
Signal
(1)
O
O
O
O
O
O
O
I
I
I
I
I
I
I/O
Transmit data 0 (2 symbols on lane 0). This bus transmits data on lane 0.
The first transmitted symbol is
transmitted symbol is
function or 8-bit PIPE mode only txdata0_ext[7:0] is available.
Transmit data control 0 (2 symbols on lane 0). This signal serves as the
control bit for
transmitted symbol and
encoding). For the x8 MegaCore function or 8-bit PIPE mode only the
single bit signal
Transmit detect receive 0. This signal is used to tell the PHY layer to start
a receive detection operation or to begin loopback.
Transmit electrical idle 0. This signal forces the transmit output to electrical
idle.
Transmit compliance 0. This signal forces the running disparity to negative
in compliance mode (negative COM character).
Receive polarity 0. This signal instructs the PHY layer to do a polarity
inversion on the 8b/10b receiver decoding block.
Power down 0. This signal requests the PHY to change it’s power state to
the specified state (P0, P0s, P1, or P2).
Receive data 0 (2 symbols on lane 0). This bus receives data on lane 0.
The first received symbol is
rxdatan_ext[15:8].
mode only
Receive data control 0 (2 symbols on lane 0). This signal is used for
separating control and data symbols. The first symbol received is aligned
with
with
mode only the single bit signal
Receive valid 0. This symbol indicates symbol lock and valid data on
rxdatan_ext
PHY status 0. This signal is used to communicate completion of several
PHY requests.
Receive electrical idle 0. This signal forces the receive output to electrical
idle.
Receive status 0: This signal encodes receive status and error codes for
the receive data stream and receiver detection.
PCI Express Compiler Version 6.1
rxdatakn_ext[0]
rxdatan_ext[1]
rxdatan_ext[7:0]
txdatan_ext
txdatakn
and
rxdatakn_ext
txdata0_ext[15:8]
txdatakn_ext[1]
. For the x8 MegaCore function or 8 Bit PIPE
For the x8 MegaCore function or 8 Bit PIPE
_
and the second symbol received is aligned
rxdatan_ext[7:0]
ext
;
Description
txdata_ext[7:0]
txdatakn_ext[0]
rxdatakn_ext
is available.
is available.
.
. For the x8 MegaCore
for the second (8b/10b
is available.
and the second is
and the second
for the first
Altera Corporation
December 2006