IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 82

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Signals
Figure 3–12. MegaCore Function I/O Signals
3–44
PCI Express Compiler User Guide
Completion Interface
Power Management
Transmit Data
Path (for VC0)
Receive Data
Path (for VC0)
Test Interface
Configuration
Interrupt
Global
tx_req0
tx_desc0
tx_ack0
tx_dfr0
tx_dv0
tx_data0[63:0]
tx_ws0
tx_cred0[21:0]
rx_req0
rx_desc0[135:0]
rx_ack0
rx_abort0
rx_retry0
rx_mask0
rx_dfr0
rx_dv0
rx_data0[63:0]
rx_be0[7:0]
rx_ws0
pme_to_cr
pme_to_sr
cfg_pmcsr[31:0]
app_msi_req
app_msi_ack
ack_msi_tc[2:0]
msi_num[4:0]
cfg_msicsr[15:0]
pex_msi_num[4:0]
app_int_sts
refclk
clk125_in
clk125_out
npor
srst
crst
12_exit
hotrst_exit
dlup_exit
cfg_tcvcmap[23:0]
cfg_busdev[12:0]
cfg_prmcfr[31:0]
cfg_devcsr[31:0]
cfg_linkcsr[31:0]
cpl_err[2:0]
cpl_pending
test_in[31:0]
test_out[511:0]
(3)
(3)
(1)
PCI Express Compiler Version 6.1
(2)
(4)
MegaCore Function
PCI Express
powerdown0_ext[1:0]
powerdown0_ext[1:0]
txcompliance0_ext
txcompliance0_ext
rxstatus0_ext[2:0]
rxstatus0_ext[2:0]
rxdata0_ext[15:0]
txdata0_ext[15:0]
txdatak0_ext[1:0]
rxdatak0_ext[1:0]
txdata0_ext[7:0]
rxdata0_ext[7:0]
txdetectrx0_ext
txdetectrx0_ext
phystatus0_ext
phystatus0_ext
txelecidle0_ext
rxelecidle0_ext
txelecidle0_ext
rxelecidle0_ext
rxpolarity0_ext
rxpolarity0_ext
txdatak0_ext
rxdatak0_ext
rxvalid0_ext
rxvalid0_ext
pipe_mode
rx[7:0]
tx[7:0]
Notes SignalChanges for x 8 MegaCore Functions:
(1) clk125_in for the x1, x4 MegaCore function
(2) clk125_out for the x1 or x4 MegaCore function
(3) srst & crst are removed for the x8 MegaCore function
(4) test_out[511:0] for the x1 or x4 MegaCore function is changed
is changed to clk250_in for a x8 MegaCore function
is changed to clk250_out for the x8 MegaCore function
to test_out[127:0] for the x8 MegaCore function.
1-Bit Serial
16-Bit PIPE for x1 and x4
(Repeated for Lanes 1 - 3
in the x4 MegaCore Function)
8-Bit PIPE for x8
(Repeated for Lanes 1 - 7
in the x8 MegaCore Function)
Altera Corporation
December 2006