IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 162

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chaining DMA Example Design
5–12
PCI Express Compiler User Guide
The software application writes these descriptor tables in the BFM shared
memory. The chaining DMA design engine continuously collects these
descriptor tables for DMA read and/or DMA write. At the beginning of
the transfer, the software application programs the DMA engine registers
with the descriptor table header. The descriptor table header contains
information such as total number of descriptor and BFM shared memory
address of the first descriptor table. When the descriptor header is set, the
chaining DMA engine continuously fetches descriptors from the BFM
shared memory for both DMA reads and DMA writes, and then performs
the data transfer for each descriptor.
Figure 5–3
an external RC CPU on the left. The block diagram contains the following
elements:
■
■
■
■
■
EP DMA write and read requester modules, mentioned just above.
An EP read/write MUX to arbitrate access to the EP memory over an
Avalon
An EP Transaction Layer Packet (TLP) translator module used to
perform TLP formatting as well as traffic management to and from
the appropriate submodule (DMA read or write configuration).
Two Root Complex (RC) memory descriptor tables, one for each
DMA module. These are described in the following section.
An RC CPU and associated PCI Express PHY link to the EP example
design, using a Root Port and a North/South Bridge.
PCI Express Compiler Version 6.1
shows a block diagram of the example design on the left and
®
-MM bus.
Altera Corporation
December 2006