IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 240

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Test-Out Interface Signals for x1 and x4 MegaCore Functions
C–10
PCI Express Compiler User Guide
txdl_sm
tx3b
tx4
tx5b
tx0
gnt
sop
eop
eot
Table C–1. test_out Signals for the x1 and x4 MegaCore Functions (Part 9 of 17)
Signal
DLL txdl
DLL txdl
DLL txdl
DLL txdl
DLL txdl
DLL txdl
DLL txdl
Subblock
282:280
283
284
292:285
293
294
295
PCI Express Compiler Version 6.1
Bit
Transmit transaction layer packet State Machine. Transmit
transaction layer packet state machine encoding:
●
●
●
●
●
●
●
This signal can be used to inject an LCRC or ECRC error.
Transaction layer packet transmitted. This signal is set on the
last DWORD of the packet where the LCRC is added to the
packet.This signal can be used to inject an LCRC or ECRC
error.
DLLP transmitted. This signal is set when a DLLP is sent to the
physical layer. This signal can be used to inject a CRC on a
DLLP.
Data link layer transmit arbitration result. This signal reports the
arbitration result between a DLLP and a transaction layer
packet:
●
●
●
●
●
●
●
●
Data link layer to PHY start of packet. This signal reports that
an SDP/STP symbol is in transition to the physical layer.
Data link layer to PHY end of packet. This signal reports that an
EDB/END symbol is in transition to the physical layer.
When sop and eop are transmitted together, it indicates that the
packet is a DLLP. Otherwise the packet is a transaction layer
packet.
Data link layer to PHY end of transmit. This signal reports that
the data link layer has finished its previous transmission and
enables the physical layer to go to low-power state or to
recovery.
000: idle
001: tlp1
010: tlp2
011: tlp3a
100: tlp5a (ECRC only)
101: tlp6a (ECRC only)
111: reserved
bit 0: InitFC DLLP
bit 1: ACK DLLP (high priority)
bit 2: UFC DLLP (high priority)
bit 3: PM DLLP
bit 4: TXN transaction layer packet
bit 5: RPL transaction layer packet
bit 6: UFC DLLP (low priority)
bit 7: ACK DLLP (low priority)
Description
Altera Corporation
December 2006