IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 151

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
December 2006
This chapter introduces the PCI Express MegaCore function testbench,
the BFM test driver module, and two example designs:
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After reviewing the components and the concepts in this chapter, you will
have the information that you need to modify the BFM test driver module
to exercise and test your own application layer design.
When you create a MegaCore function variation as described in
“Generate Files” on page
customized to your variation also is generated.
The testbench instantiates an example design and a root port BFM, which
provides the following configuration routine and interface:
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The testbench uses test driver modules (altpcietb_bfm_driver for the
simple DMA design and altpcietb_bfm_driver_chaining for the
chaining DMA design) to exercise the example design’s target memory
and DMA channel. This test driver module also displays information
from the endpoint’s configuration space registers which lets you verify
the parameters you specified in the MegaWizard interface.
Using one of the provided example designs as a sample, you can easily
modify the testbench test driver module to use your own application
layer design instead of the provided example design’s application layer
logic. The testbench and root port BFM design simplifies the process of
exercising the application layer logic that interfaces to the MegaCore
function endpoint variation. PCI Express link monitoring and error
injection capabilities are limited to those provided by the MegaCore
function’s test_in and test_out signals. The following sections
describe the testbench, two example designs, and root BFM in detail.
A simple DMA example design
A chaining DMA example design
A configuration routine that sets up all the basic configuration
registers in the endpoint. This allows the endpoint application to be
the target of and initiate PCI Express transactions.
A VHDL/Verilog HDL procedure interface to initiate PCI Express
transactions to the endpoint.
PCI Express Compiler Version 6.1
2–11, an example design and testbench,
Example Designs
5. Testbench &
5–1