IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 74

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Parameter Settings
3–36
PCI Express Compiler User Guide
Subsystem ID
Subsystem vendor ID
Link common clock
Implement advanced
error reporting
Implement ECRC check
Implement ECRC
generation
Link port number
Tags supported
MSI messages requested 1, 2, 4, 8, 16,
MSI message 64-bit
capable
Table 3–19. Capabilities Page Parameters (Part 2 of 2)
Parameter
16-bit Hex
16-bit Hex
On/Off
On/Off
On/Off
On/Off
8-bit Hex
4, 8, 16, 32,
64, 128, 256
32
On/Off
Value
PCI Express Compiler Version 6.1
Sets the read-only value of the subsystem device ID register.
Sets the read-only value of the subsystem vendor ID register. This
parameter can not be set to 0xFFFF per the PCI Express
Specification.
Indicates if the common reference clock supplied by the system is
used as the reference clock for the PHY. This parameter sets the
read-only value of the slot clock configuration bit in the link status
register.
Implement the advanced error reporting capability.
Enable ECRC checking capability. Sets the read-only value of the
ECRC check capable bit in the advanced error capabilities and
control register. This parameter requires you to implement the
advanced error reporting capability.
Enable ECRC generation capability. Sets the read-only value of the
ECRC generation capable bit in the advanced error capabilities and
control register. This parameter requires you to implement the
advanced error reporting capability.
Sets the read-only values of the port number field in the link
capabilities register.
Indicates the number of tags supported for non-posted requests
transmitted by the application layer. The transaction layer tracks all
outstanding completions for non-posted requests made by the
application. This parameter configures the transaction layer for the
maximum number to track. The Application Layer must set the Tag
values in all Non-Posted PCI Express headers to be less than this
value. Values greater than 32 also set the Extended Tag Field
Supported bit in the configuration space device capabilities register.
The application can only use tag numbers greater than 31 if
configuration software sets the Extended Tag Field Enable bit of the
device control register. This bit is available to the application as
cfg_devcsr[8]
MegaCore function.
Indicates how many messages the application requests. Sets the
value of the multiple message capable field of the message control
register. See
information.
Indicates whether the MSI capability message control register is 64-
bit addressing capable. PCI Express native endpoints always support
MSI 64-bit addressing.
“MSI & INTx Interrupt signals” on page 3–82
. This value is limited to a maximum of 8 for the x8
Description
Altera Corporation
December 2006
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