IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 93

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Figure 3–16. Transaction Layer Not Ready to Accept Packet
Altera Corporation
December 2006
Descriptor
Signals
Signals
Data
tx_desc[127:0]
tx_data[63:32]
tx_data[31:0]
tx_ack
tx_req
tx_ws
tx_err
tx_dfr
tx_dv
1
Figure 3–16
acknowledge before write data can be transferred.
Possible Wait State Insertion
If the MegaCore function is not initialized with its maximum potential
lanes, data transfer is necessarily hindered. See
application transmits a 32-bit memory write transaction of 8 DWORDS.
Address bit 2 is set to 0.
In clock cycle 3, data transfer can begin immediately as long as the
transfer buffer is not full.
In clock cycle 5, once the buffer is full and the MegaCore function
implements wait states to throttle transmission; 4 clock cycles are
required per transfer instead of 1 because the MegaCore function is not
configured with the maximum possible number of lanes implemented.
Figure 3–17
asserting the wait state signal.
X
X
2
PCI Express Compiler Version 6.1
3
4
shows that the application layer must wait to receive an
shows how the transaction layer extends the a data phase by
MEMWR32
5
DW0
6
7
Clock Cycles
8
9
10
PCI Express Compiler User Guide
11
X
X
12
Figure
13
14
3–18. The
15
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