IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 225

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
December 2006
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Table A–2. Configuration Signals for x8 MegaCore Functions
Signal
Power
Management:
N_FTS
Separate
Power
Management:
N_FTS
Common
Capabilities:
Link Port
Number
Fixed to 0
Fixed to 0
Fixed to 0
Capabilities:
MSI Messages
Requested
Capabilities:
MSI Message
64 bit Capable
Capabilities:
MSI Per Vector
Masking
System: BAR
Table (BAR0)
System: BAR
Table (BAR1)
System: BAR
Table (BAR2)
System: BAR
Table (BAR3)
System: BAR
Table (BAR4)
Value or Wizard
Page/Label
PCI Express Compiler Version 6.1
Number of fast training sequences needed in separate clock
mode (N_FTS).
Number of fast training sequences needed in common clock
mode (N_FTS).
Link capabilities register: port number.
Reserved.
Reserved.
Reserved.
MSI capability message control register: multiple message
capable request field. 0 = 1 message, 1 = 2 messages, 2 = 4
messages, 3 = 8 messages, 4 = 16 messages, 5 = 32 messages.
MSI capability message control register: 64-bit capable. 0 = 32b,
1 = 64b or 32b.
Per-bit vector masking (RO field).
BAR0 size mask and read only fields (I/O space, memory space,
prefetchable). bit 31 - 4 = size mask, bit 3 = prefetchable, bit 2 =
64 bit, bit 1 = 0, bit 0 = I/O.
BAR1 size mask and read only fields (I/O space, memory space,
prefetchable). bit 31 - 4 = size mask, bit 3 = prefetchable, bit 2 =
64 bit, bit 1 = 0, bit 0 = I/O (or bit 31 - 0 = size mask if previous 64
bit).
BAR2 size mask and read only fields (I/O space, memory space,
prefetchable). bit 31 - 4 = size mask, bit 3 = prefetchable, bit 2 =
64 bit, bit 1 = 0, bit 0 = I/O.
BAR3 size mask and read only fields (I/O space, memory space,
prefetchable). bit 31 - 4 = size mask, bit 3 = Prefetchable, bit 2 =
64 bit, bit 1 = 0, bit 0 = I/O (or bit 31 - 0 = size mask if previous 64
bit).
BAR4 size mask and read only fields (I/O space, memory space,
prefetchable). bit 31 - 4 = size mask, bit 3 = prefetchable, bit 2 =
64 bit, bit 1 = 0, bit 0 = I/O.
Description
PCI Express Compiler User Guide
A–9