IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 101

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Altera Corporation
December 2006
Notes for
(1) where n is the virtual channel number; For x1 and x4, n can be 0 - 3
(2) For x8, n can be 0 or 1
rx_ackn
(1)
rx_abortn
(1)
rx_retryn
(1)
rx_maskn
(1)
Table 3–27. Standard Descriptor Phase Signals (Part 2 of 2)
,
,
,
,
(2)
(2)
(2)
(2)
Signal
Table 3–27
I
I
I
I
I/O
The MegaCore function generates the eight MSBs of this signal with BAR
decoding information. See
Receive acknowledge. This signal is asserted for 1 clock cycle when the
application interface acknowledges the descriptor phase and starts the data
phase, if any. The
the
Receive abort. This signal is asserted by the application interface if the
application cannot accept the requested descriptor. In this case, the descriptor is
removed from the receive buffer space, flow control credits are updated, and, if
necessary, the application layer generates a completion transaction with
unsupported request (UR) status on the transmit side.
Receive retry. The application interface asserts this signal if it is not able to
accept a non-posted request. In this case, the application layer must assert
rx_mask0
transactions are presented on the receive interface for the duration of
rx_mask0
Receive mask (non-posted requests). This signal is used to mask all non-posted
request transactions made to the application interface to present only posted and
completion transactions. This signal must be asserted with
deasserted when the MegaCore function can once again accept non-posted
requests.
Table 3–28. rx_desc[135:128]: Descriptor & BAR Decoding
rx_desc
128
129
130
131
132
133
134
135
Bit
PCI Express Compiler Version 6.1
.
along with
is ready for the next transmission.
= 1: BAR 0 decoded
= 1: BAR 1 decoded
= 1: BAR 2 decoded
= 1: BAR 3 decoded
= 1: BAR 4 decoded
= 1: BAR 5 decoded
= 1: Expansion ROM decoded
Reserved
rx_req
rx_retry0
signal is deasserted on the following clock cycle and
Table
Description
Type 0 Component
3–28.
so that only posted and completion
PCI Express Compiler User Guide
rx_retry0
and
3–63