IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 99

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Figure 3–23. Error Assertion Waveform
Altera Corporation
December 2006
Descriptor
Signals
Signals
Data
tx_desc[127:0]
tx_data[63:32]
tx_data[31:0]
tx_ack
tx_req
tx_ws
tx_err
tx_dfr
tx_dv
Error Asserted & Transmission Is Nullified
In this example, the application transmits a 64-bit memory write
transaction of 14 DWORDS. Address bit 2 is set to 0. See
In clock cycle12, tx_err is asserted which nullifies transmission of the
transaction layer packet on the link. Nullified packets have the LCRC
inverted from the calculated value and use the end bad packet (EDB)
control character instead of the normal END control character.
Receive Interface Operation Signals
The receive interface, like the transmit Interface, is based on two
independent busses, one for the descriptor phase (rx_desc[135:0])
and one for the data phase (rx_data[63:0]). Every transaction
includes a descriptor. A descriptor is a standard transaction layer packet
header as defined by the PCI Express Base Specification Revision 1.0a with
two exceptions. Bits 126 and 127 indicate the transaction layer packet
group and bits 135:128 describe BAR and address decoding information
(see rx_desc[135:0] below for details).
Receive Data Path Signals
Receive data path signals can be divided into two groups:
■
■
1
Descriptor phase signals
Data phase signals
PCI Express Compiler Version 6.1
2
MEMWR64
3
DW1
DW0
4
5
DW3
DW2
6
DW5
DW4
Clock Cycles
7
DW7
DW6
8
DW9
DW8
9
DWB
DWA
10
PCI Express Compiler User Guide
DWD
DWC
11
DWF
DWE
12
13
14
Figure
15
3–23.
3–61