peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 106

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

For some applications it might be useful starting of jitter attenuation at lower frequencies.
Therefore the corner frequency is switchable by the factor of ten down to 0.6 Hz
(LIM2.SCF).
Jitter attenuation can be achieved either using an external tunable crystal on pins
XTAL1/XTAL2 or using the crystal-less jitter attenuation selected by LIM2.DJA1/2. In this
case, a stable clock or regular crystal of 16.384 MHz has to be provided on pin XTAL1
(+/- 50 ppm). In crystal-less mode the system clock output on pin CLK16M can be either
the dejittered or the non-dejittered clock (LIM3.CSC).
The DCO-R circuitry is automatically centered to the nominal bit rate if the reference
clock on pin SYNC/RCLK is missed for two 2.048 or 1.544-MHz clock periods. In analog
line interface mode the RCLK is always running. Only in digital line interface mode with
single rail data (NRZ) a gapped clock on pin RCLK may occur.
The receive jitter attenuator works in two different modes:
• Slave mode
• Master mode
The following table shows the clock modes with the corresponding synchronization
sources.
Table 23
Mode
Master
Master
Master
Slave
Slave
Data Sheet
In Slave mode (LIM0.MAS = 0) the DCO-R is synchronized with the recovered route
clock. In case of LOS the DCO-R switches to Master mode automatically.
In Master mode (LIM0.MAS = 1) the jitter attenuator is in free running mode if on pin
SYNC no clock is supplied. If an external clock on the SYNC input is applied, the DCO-
R synchronizes to this input. The external frequency can be 1.544 MHz
(LIM1.DCOC=0) or 2.048 MHz (LIM1.DCOC=1).
Internal
LOS Active
independent Fixed to
independent 1.544 MHz Synchronized with SYNC input
independent 2.048 MHz Synchronized with SYNC input
no
no
System Clocking (T1/J1)
SYNC
Input
VSS
Fixed to
VSS
1.544 MHz
or
2.048 MHz
System Clocks
free running (oscillator centered)
(LIM1.DCOC=0)
(LIM1.DCOC=1)
Synchronized with Line RCLK
Synchronized with Line RCLK
106
Functional Description T1/J1
FALC-LH V1.3
PEB 2255
2000-07