peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 211

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

XLU…
CMI…
SA6SY…
CFRZ…
EXTIW…
Data Sheet
Transmit LLB UP Code
0…
1…
Select CMI Precoding
Only valid if CMI code (FMR0.XC1/0=01) is selected. This bit defines
the CMI precoding and influences only the transmit data and not the
receive data.
0…
1…
Only valid if multiframe format (FMR2.RFS1/0=1x) is selected.
0…
1…
Enable CAS Freeze Output
This bit selects the function of pin RFSPQ.
0…
1…
Extended CRC4 to Non CRC4 Interworking
Only valid in multiframe format. This bit selects the reaction of the
synchronizer after the 400 ms timeout has been elapsed and starts
transmitting a remote alarm if FMR2.AXRA is set.
0…
Receive SA6 Access Synchronous Mode
LCR1.LLBF. For correct operation bit FMR3.XLU must be
cleared.
Normal operation.
A one in this bit position causes the transmitter to replace
normal transmit data with the LLB UP Code continuously until
this bit is reset. The LLB UP Code is overwritten by the timeslot
0 depending on bit LCR1.LLBF. For correct operation bit
FMR3.XLD must be cleared.
CMI with HDB3 precoding
CMI without HDB3 precoding
The detection of the predefined SA6 bit pattern (refer to chapter
SA6 Bit Detection according to ETS 300233) is done
independently of the multiframe synchronous state.
The detection of the SA6 bit pattern is done synchronously to
the multiframe.
The receive frame synchronous pulse is output on pin RFSPQ.
The synchronous status of the integrated CAS controller
(FRS1.TS16LFA) is output on pin RFSP. If the CAS
synchronizer lost its synchronization this pin is set high.
The CRC4 to Non CRC4 interworking is done as described in
ITU-T G. 706 Annex B.
211
FALC-LH V1.3
E1 Registers
PEB 2255
2000-07