peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 53

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Figure 10
Test handling is performed via the pins TCK (Test Clock), TMS (Test Mode Select), TDI
(Test Data Input) and TDO (Test Data Output). Test data at TDI are loaded with a 4-MHz
clock signal connected to TCK. ‘1’ or ‘0’ on TMS causes a transition from one controller
state to an other; constant ’1’ on TMS leads to normal operation of the chip.
If no boundary scan testing is planned TMS and TDI do not need to be connected since
pull-up transistors ensure high input levels in this case. After switching on the device
(power-on), a reset signal is generated internally, which forces the TAP controller into
test logic reset state.
Data Sheet
TCK
TMS
TDO
TDI
CLOCK
Test
Control
Data IN
Enable
Data OUT
Block Diagram of Test Access Port and Boundary Scan
Test Access Port
Generation
Clock
-Finite State Machine
-Instruction Register (3 bits)
-Test Signal Generator
CLOCK
TAP Controller
53
Power ON
Reset
Reset
Functional Description E1/T1/J1
BS Data IN
Control Bus
ID Data OUT
SS Data OUT
6
FALC-LH V1.3
PEB 2255
1
2000-07
2
n
ITB09842
Pins