peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 301

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

SXSC…
XBS1…0…
System Interface Control 2 (Read/Write)
Value after RESET: 00
FFS…
Data Sheet
SIC2
FFS
7
Select Transmit System Clock
0…
1…
00… By-pass of transmit elastic store (SCLKX=1.544 MHz) or
01… Buffer size: 1 frame
10… Buffer size: 2 frames
11… Buffer size: 92 bits
Force Freeze Signaling
Setting this bit disables updating of the receive signaling buffer and
current signaling information is frozen. After resetting this bit and
receiving a complete superframe updating of the signaling buffer is
Transmit Buffer Size
SSF
H
Input frequency on pin SCLKX: 8.192 MHz
Calculation of delay time T (SCLKX cycles) depends on the
value X of the “Transmit Counter Offset” register XC1/0 and of
the programming of XC1.XCOS:
Delay T is an even number in the range of 0 to 1022:
XCOS = 0: X = 498 -T/2 if
input frequency on pin SCLKX: 1.544 MHz
Calculation of delay time T (SCLKX cycles) depends on the
value X of the “Transmit Counter Offset” register XC1/0:
T = (380
Delay time T = time between beginning of time-slot 0 at XDI
and the initial edge of SCLKX after SYPX goes active.
If this bit is set FMR1.IMOD must be set also and bit XC0.0
should be cleared.
1 frame (SCLKX = 8.192MHz)
Delay T is an odd number in the range of 1 to 1023:
XCOS = 1: X = 498-(T-1)/2 if
X = 1010 - T/2 if
X = 1010 - (T-1)/2 if
x/2) mod 193
301
0
998
1
T
999
T
T
996
T
1022
997
1023
FALC-LH V1.3
T1/J1 Registers
SRFSO
0
PEB 2255
2000-07
(3D)