peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 61

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

PEB 2255
FALC-LH V1.3
Functional Description E1
4.1.9
Transmit Jitter Attenuator (E1)
The transmit jitter attenuator DCO-X circuitry generates a “jitter free“ transmit clock and
meets the following requirements: ITU-T I.431, G. 703, G. 736-739, G.823 and ETSI
TBR12/13. The DCO-X circuitry works internally with the same high frequency clock as
the receive jitter attenuator it does. It synchronizes either to the working clock of the
transmit backplane interface or the clock provided by pin SYNC2 or the receive clock
RCLK (remote loop/loop-timed). The DCO-X attenuates the incoming clock jitter starting
at 6 Hz with 20 dB per decade fall off. With the jitter attenuated clock, which is directly
dependent on the phase difference of the incoming clock and the jitter attenuated clock,
data is read from the transmit elastic buffer or from the JATT buffer (remote loop with
JATT). Wander with a jitter frequency below 6 Hz is passed transparently.
The DCO-X accepts gapped clocks which are used in ATM or SDH/SONET applications.
The jitter attenuated transmit clock is output by pin XCLK.
In the loop-timed clock configuration (LIM2.ELT) the DCO-X circuitry generates a
transmit clock which is frequency synchronized with RCLK. In this configuration the
transmit elastic buffer has to be enabled.
DCO-X can optionally be used with XTAL1 clock reference (selected by
LIM1.TCD1 = 1). The dejittered transmit clock can be output on pin CLK16M. In this case
the clocks CLKX, CLK8 and FSC are not synchronized with RCLK/SYNC.
Data Sheet
61
2000-07