peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 324

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

RAB…
HA1...0…
HFR …
Note: Bits RSIS.7...2 and RSIS.0 are not valid with a BOM frame. This means, if HFR=0,
LA …
Data Sheet
all other bits of RSIS have to be ignored
The received frame was aborted from the transmitting station.
According to the HDLC protocol, this frame must be discarded by the
receiver station.
Significant only if 2-byte address mode has been selected.
In operating modes which provide high byte address recognition, the
FALC
contents of two individually programmable registers (RAH1, RAH2)
and the fixed values FE
Dependent on the result of this comparison, the following bit
combinations are possible (SS7 support not active):
Note: If RAH1, RAH2 contain identical values, a match is indicated
HDLC Frame Format
0
1
Low Byte Address Compare
Significant in HDLC modes only.
The low byte address of a 2-byte address field, or the single address
byte of a 1-byte address field is compared with two registers. (RAL1,
RAL2).
0
1
Receive Message Aborted
High Byte Address Compare
00… RAH2 has been recognized
01… Broadcast address has been recognized
10… RAH1 has been recognized C/R = 0 (bit 1)
11… RAH1 has been recognized C/R = 1 (bit 1)
®
A BOM frame was received.
A HDLC frame was received.
RAL2 has been recognized
RAL1 has been recognized
-LH compares the high byte of a 2-byte address with the
by ‘10’ or ‘11’.
324
H
and FC
H
(broadcast address).
FALC-LH V1.3
T1/J1 Registers
PEB 2255
2000-07