peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 275

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

CRC…
ECM…
IMOD…
XAIS…
Data Sheet
Enable CRC6
This bit is only significant when using the ESF format.
0
1
Error Counter Mode
The function of the error counters (FEC,CEC,CVC,EBC) is
determined by this bit.
0
1…
System Interface Mode
0…4.096 Mbit/s
1…2.048 Mbit/s or 1.544 Mbit/s
This bit has to be set if SIC1.SRSC or SIC1.SXSC are set.
Transmit AIS Towards Remote End
Sends AIS (blue alarm) via ports: XL1, XL2 towards the remote end.
If Local Loop Mode is enabled the transmitted data is looped back to
the system internal highway without any changes.
CRC6 check/generation disabled. For transmit direction, all
CRC bit positions are set.
CRC6 check/generation enabled.
Before reading an error counter the corresponding bit in the
Disable Error Counter register (DEC) has to be set. In 8 bit
access the low byte of the error counter should always be read
before the high byte. The error counters are reset with the rising
edge of the corresponding bits in the DEC register.
Every second the error counter is latched and then
automatically be reset. The latched error counter state should
be read within the next second. Reading the error counter
during updating should be avoided (do not access an error
counter within 2 µs before or after the one-second interrupt
occurs).
275
FALC-LH V1.3
T1/J1 Registers
PEB 2255
2000-07