peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 132

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

• Reporting and controlling of slips
Writing of received data from XDI is controlled by SCLKX and SYPX/XMFS in
conjunction with the programmed offset values for the transmit time slot/clock slot
counters. Reading of stored data is controlled by the clock generated by DCO-X circuitry
and the transmit framer. With the dejittered clock data is read from the transmit elastic
buffer and are forwarded to the transmitter. Reporting and controlling of slips is
automatically done according to the receive direction. Positive/negative slips are
reported in interrupt status bits ISR5.XSP and ISR5.XSN.
A re-initialization of the transmit memory is done by re-programming the transmit time
slot counter XC1 and with the next SYPX pulse. After that, this memory has its optimal
start position.
The frequency of the working clock for the transmit system interface is programmable by
SIC1.SXSC and SIC1.SRSC to be 1.544 or 8.192 MHz.
Generally the data or marker on the system interface are clocked off or latched on the
falling edge of the SCLKX clock.
The following table gives an overview of the transmit buffer operating modes.
Table 29
SIC1.XBS1...0
00
SCLKX=1.544 MHz
00
SCLKX=8.192 MHz
01
10
11
1)
Data Sheet
compatible with FALC
Transmit Buffer Operating Modes (T1/J1)
®
54
Buffer Size
bypass
1 frame
short buffer
1 frame
2 frames
132
TS Offset
programming
enabled
enabled
enabled
enabled
enabled
Functional Description T1/J1
Slip performance
no
yes
yes
yes
yes
If XSW.XTM = 1,
slip is performed on
the frame boundary
1)
FALC-LH V1.3
PEB 2255
2000-07