peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 221

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

System Interface Control 1 (Read/Write)
Value after RESET: 00
SRSC…
RBS1...0…
Data Sheet
SIC1
SRSC
7
0…
1…
00… buffer size : 2 frames
01… buffer size : 1 frame
10… buffer size : 92 bits
11… bypass of receive elastic store
Select Receive System Clock
Receive Buffer Size
H
Calculation of delay time T (SCLKR cycles) depends on the
value X of the “Receive Counter Offset” register RC1/0 and of
the programming of RC0.RCOS.
Delay T is an even number in the range of 0 to 1022:
RCOS = 0: X = 5
Calculation of delay time T (SCLKR cycles) depends on the
value X of the “Receive Counter Offset” register RC1/0:
T = (260
Delay time T = time between beginning of time slot 0 at RDO
and the initial edge of SCLKR after SYPR goes active.
If this bit is set FMR1.IMOD must be set also and bit RC0.0
must be cleared.
Delay T is an odd number in the range of 1 to 1023:
RCOS = 1: X = 5
expected frequency on pin SCLKR: 8.192 MHz
expected frequency on pin SCLKR: 2.048 MHz
RBS1
X = 517
X = 517
x/2) mod 256
RBS0
221
T/2 if
(T
SXSC
T/2 if
(T
1)/2 if
1)/2 if
0
12
T
1
T
13
10
T
1022
T
XBS1
11
1023
FALC-LH V1.3
XBS0
E1 Registers
0
PEB 2255
2000-07
(3C)