peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 117

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

•
Table 27
System Data Rate
1.544 Mbit/s
2.048 Mbit/s
4.096 Mbit/s
x = valid, -- = invalid
Generally the data or marker on the system interface are clocked off or latched on the
falling edge of the SCLKR/SCLKX clock independently.
The signal on pin SYPR in conjunction with the assigned timeslot offset in register RC0
and RC1 define the beginning of a frame on the receive system highway.
The signal on pin SYPX in conjunction with the assigned timeslot offset in register XC0
and XC1 define the beginning of a frame on the transmit system highway.
Adjusting the frame begin (time slot 0, bit 0) relative to SYPR/X is possible in the range
of 0...125 µsec.
A receive frame marker RFM can be activated (SIC2.SRFSO = 1) during any bit position
of the entire frame. Programming is done with registers RC1/0. The receive frame
marker is active high for one 1.544/2.048 MHz cycle and is clocked off with the falling
edge of the clock which is input on port SCLKR or RCLK.
Data Sheet
System Clock and Data Rates (T1/J1)
Clock Rate 1.544 MHz
117
--
--
x
Functional Description T1/J1
Clock Rate 8.192 MHz
FALC-LH V1.3
--
x
x
PEB 2255
2000-07