peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 254

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

LOS…
RAR…
RA…
Interrupt Status Register 3 (Read)
All bits are reset when ISR3 is read.
If bit IPC.VIS is set, interrupt statuses in ISR3 may be flagged although they are masked
via register IMR3. However, these masked interrupt statuses neither generate a signal
on INT, nor are visible in register GIS.
ES…
SEC…
Data Sheet
ISR3
ES
7
This bit is set when a loss of signal alarm is detected in the received
bit stream and FRS0.LOS is set. It is set during alarm simulation.
If IPC.SCI is set high this interrupt status bit is set with every change
of state of FRS0.LOS.
Set if a remote alarm in TS0 is cleared and bit FRS0.RA is reset. It is
set also after alarm simulation is finished and no remote alarm is
detected.
Remote Alarm
Set if a remote alarm in TS0 is detected and bit FRS0.RA is set. It is
set during alarm simulation.
Errored Second
This bit is set if at least one enabled interrupt source via IMR4 is set
during the time interval of one second. Interrupt sources of IMR4
register:
LFA = Loss of frame alignment detected (FRS0.LFA)
FER = Framing error received
CER = CRC error received
AIS = Alarm indication signal (FRS0.AIS)
LOS = Loss of signal (FRS0.LOS)
CVE = Code violation detected
SLIP= Receive Slip positive/negative detected
EBE = E-Bit error detected (RSP.RS13/15)
Second Timer
The internal one second timer has expired. The timer is derived from
clock RCLK.
Loss of Signal
Remote Alarm Recovery
SEC
LMFA16
AIS16
254
RA16
API
RSN
FALC-LH V1.3
RSP
E1 Registers
0
PEB 2255
2000-07
(6B)