peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 163

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

7
7.1
The FALC
T1/J1 mode. There are only minor differences between T1 and J1 mode which are
described in
The device is programmable via a microprocessor interface which enables byte or word
access to all control and status registers.
After reset the FALC
described in sections
Initialization in T1/J1 Mode” on page 163
The status registers are read-only and are updated continuously. Normally, the
processor reads the status registers periodically to analyze the alarm status and
signaling data.
7.2
The FALC
minimum period of 20 µs. During reset the FALC
SCLKR, SCLKX, XTAL1 and XTAL3. All output stages except of CLK16M, CLK12M,
CLK8M, CLKX, FSC, XCLK and RCLK are in a high impedance state, all internal flip-
flops are reset and most of the control registers are initialized with default values.
SIgnals (for example RL1/2 receive line) should not be applied before the device is
powered up.
After reset the device is initialized to E1 operation. Switching to T1/J1 mode is done by
software (FMR1.PMOD = 1).
7.3
After reset, the FALC
mode, bit FMR1.PMOD has to be set high. After the internal clocking is settled to T1/
J1mode (takes up to 20 µs), the following register values are initialized:
Data Sheet
®
®
Operational Description T1/J1
Operational Overview T1/J1
-LH in principle can be operated in two modes, which are either E1 mode or
Device Reset T1/J1
Device Initialization in T1/J1 Mode
-LH is forced to the reset state if a high signal is input on pin RES for a
Table
48.
®
-LH must be initialized first. General guidelines for initialization are
®
“Device Initialization in E1 Mode” on page 158
-LH is initialized for E1 doubleframe format. To initialize T1/J1
163
®
-LH needs an active clocks on pins
Operational Description T1/J1
FALC-LH V1.3
and
PEB 2255
“Device
2000-07