peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 282

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

XLU…
SRO…
XTM…
RTF…
Data Sheet
Transmit LLB UP Code
0…
1…
Valid in F12/F72 and ESF frame format only
0…
reordering of ABCD bits.
1…
Transmit Transparent Mode
Valid if loop-timed mode is enabled (LIM2.ELT = 1).
0…Ports SYPX/XMFS define the frame/multiframe begin on the
transmit system highway. The transmitter is usually synchronized on
this externally sourced frame boundary and generates the FAS bits
according to this framing. Any change of the transmit time slot
assignment or a transmit slip subsequently produces a change of the
FAS bit positions.
1… Disconnects the control of the transmit system interface from the
transmitter. The transmitter is now in a free running mode without any
possibility to update the multiframe position. The framing (FAS bits)
generated by the transmitter is not disturbed (in case of changing the
transmit time slot assignment or transmit slip) by the transmit system
highway unless register XC1 is written. Useful in loop-timed
applications. For correct operation the transmit elastic buffer (2
frames, SIC1.XBS1/0= 10) has to be enabled
Setting this bit all 193 bits per frame of the incoming multiframe are
forwarded to pin RDO transparently. In asynchronous state the
received data may be transparently switched through if bit
FMR2.DAIS is set.
Signaling Register Organization
Receive Transparent Forwarding
For details see description of registers XS1...12 on page
RS1...12 on page
Normal operation.
A one in this bit position causes the transmitter to replace
normal transmit data with the LLB UP (activate) Code
continuously until this bit is reset. The LLB UP Code is
optionally overwritten by the framing/DL/CRC bits. For correct
operation bit FMR5.XLD must be cleared.
Signaling access via registers RS/XS1...12 is done without
Signaling access via registers RS/XS1...12 is done with
reordering of ABCD bits.
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282
FALC-LH V1.3
T1/J1 Registers
PEB 2255
305
2000-07
and