peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 67

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

PEB 2255
FALC-LH V1.3
Functional Description E1
The complete CAS multiframe can be transmitted on pin RSIG. The signaling data is
clocked with the working clock of the receive highway in conjunction with the receive
synchronization pulse (SYPR/RFM). Data on RSIG is transmitted in the last 4 bits per
time slot and are aligned to the data on RDO. The first 4 bits per time slot can be
optionally fixed high or low, except for time slot 0 and 16. In time slot 0 the FAS/NFAS
word is transmitted, in time slot 16 the CAS multiframe pattern. Data on RSIG is valid
only if the freeze signaling status is inactive. In case of freeze status, old data are
repeated. With FMR1.SAIS = 1 an all-ones data stream may be transmitted on RDO and
RSIG.
The signaling procedure is done as it is described in ITU-T G.704 and G.732.
The main functions are:
• Synchronization to a CAS multiframe
• Detection of AIS and remote alarm in CAS multiframes
• Separation of CAS service bits
Updating of the receive signaling information is controlled by the freeze signaling status.
The freeze signaling status is output on pin RFSP/FREEZS and is generated, if:
• Bit FRS1.TSL16LFA = 1 or
• FRS0.LOS=1 or
• a receive slip occurred
The receive signaling buffer is updated if the alarm remains inactive for at least one
complete CAS multiframe. Setting of bit SIC2.FFS forces the freeze status active. The
current freeze status could be read in register SIS.SFS. Optionally automatic freeze
signaling may be disabled by setting bit SIC3.DAF.
The CAS controller acts on the PCM highway side of the receive buffer. Therefore slips
disturb CAS data.
Data Sheet
67
2000-07