peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 290

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Transmit DL-Bit Register 1...3 (Read/Write)
Value after RESET: 00
XDL1…XDL3…
Clear Channel Register (Read/Write)
Value after RESET: 00
CH1…CH24…
Data Sheet
CCB1
CCB2
CCB3
XDL1
XDL2
XDL3
XDL17
XDL27
XDL37
CH17
CH1
CH9
7
7
Transmit FS/DL-Bit Data
The DL-bit register access is enabled by setting bits FMR1.EDL = 1.
With the transmit multiframe begin an interrupt ISR1.XMB is
generated and the contents of these registers XDL1...3 is copied into
a shadow register. The contents is sent out subsequently in the data
stream of the next outgoing multiframe if no transparent mode is
enabled. XDL10 is sent out first.
In F4 frame format only XDL10...11 are transmitted. In F24 frame
format XDL10...23 are shifted out. In F72 frame format XDL10...37
are transmitted.
The transmit multiframe begin interrupt (XMB) requests that these
registers should be serviced. If requests for new information are
ignored, current contents is repeated.
XDL16
XDL26
XDL36
Channel Selection Bits
0…
1…
CH10
CH18
CH2
H
H
, 00
, 00
Normal operation. Bit-robbing information and Zero Code
Suppression (ZCS, B7 stuffing) may change contents of the
selected speech/data channel if assigned modes are enabled
via bits FMR5.EIBR and FMR0.XC1/0.
Clear channel mode. Contents of selected speech/data
channel is not overwritten by internal or external bit-robbing and
XDL15
XDL25
XDL35
H
H
CH11
CH19
CH3
, 00
, 00
H
H
XDL14
XDL24
XDL34
CH12
CH20
CH4
290
XDL13
XDL23
XDL33
CH13
CH21
CH5
XDL12
XDL22
XDL32
CH14
CH22
CH6
XDL11
XDL21
XDL31
CH15
CH23
CH7
FALC-LH V1.3
T1/J1 Registers
XDL10
XDL20
XDL30
CH16
CH24
CH8
0
0
PEB 2255
2000-07
(2C)
(2D)
(2A)
(2B)
(2E)
(2F)