peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 65
peb2255
Manufacturer Part Number
peb2255
Description
E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB2255.pdf
(374 pages)
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In single frame mode ( SIC1. RBS), values of receive time slot offset (RC1/0) have to be
specified great enough to prevent too great approach of frame begin (line side) and
frame begin (system side).
Figure 16
A slip condition is detected when the write pointer (W) and the read pointer (R) of the
memory are nearly coincident, i.e. the read pointer is within the slip limits (S +, S –). If a
slip condition is detected, a negative slip (one frame or one half of the current buffer size
is skipped) or a positive slip (one frame or one half of the current buffer size is read out
twice) is performed at the system interface, depending on the difference between RCLK
and the current working clock of the receive backplane interface. i.e. on the position of
pointer R and W within the memory. A positive/negative slip is indicated in the interrupt
status bits ISR3.RSP and ISR3.RSN.
•
Figure 16
Data Sheet
gives an idea of operation of the receive elastic buffer:
The Receive Elastic Buffer as Circularly Organized Memory
S+, S-
W :
R
:
:
Frame 2 Time Slots
Write Pointer (Route Clock controlled)
Read Pointer (System Clock controlled)
Limits for Slip Detection (mode dependent)
R
S-
65
R’
W
S+
Slip
Frame 1 Time Slots
Moment of Slip Detection
Functional Description E1
ITD10952
FALC-LH V1.3
PEB 2255
2000-07
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