peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 189

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Common Configuration Register 3 (Read/Write)
Value after RESET: 00
Note: Unused bits have to be cleared.
PRE1...0…
EPT…
Note: The ’Shared Flag’ feature is not influenced by preamble transmission.
Data Sheet
CCR3
Zero bit insertion is disabled during preamble transmission.
PRE1
7
Note: It is seen that changing the value of RFT1, 0 is possible even
RFT1
0
0
1
1
If preamble transmission is enabled, the preamble defined by register
PRE is transmitted:
00... 1 time
01... 2 times
10... 4 times
11... 8 times
This bit enables transmission of preamble. The preamble is started
after interframe timefill transmission has been stopped and a new
frame is to be transmitted. The preamble consists of an 8-bit pattern
repeated a number of times. The pattern is defined by register PRE,
the number of repetitions is selected by bits PRE0 and PRE1.
Number of Preamble Repetitions
Enable Preamble Transmission
PRE0
H
during the reception of one frame. The total length of the
received frame can be always read directly in RBCL, RBCH
after a RPF interrupt, except when the threshold is increased
during reception of that frame. The real length can then be
inferred by noting which bit positions in RBCL are reset by a
RMC command (see table below):
EPT
RFT0
0
1
0
1
RADD
189
Bit Positions in RBCL Reset by a
CMDR.RMC Command
RBC4 .… 0
RBC3 … 0
RBC1,0
RBC0
RCRC
XCRC
FALC-LH V1.3
E1 Registers
0
PEB 2255
2000-07
(0A)