peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 215

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

TCD1…
JATT…RL...
DRS…
Data Sheet
Transmit Clock Generation DCO-X
0…
1…
Transmit Jitter Attenuator/Remote Loop
00… Normal operation. The transmit jitter attenuator is disabled.
01… Remote Loop active without transmit jitter attenuator enabled.
10… Transmit Slicer active.
11… Remote Loop and jitter attenuator active. Received data from
0…
1…
Dual Rail Select
The transmit clock is sourced by the DCO-X circuitry, if the
transmit elastic buffer is enabled. Reference clock is XTAL3.
The transmit clock is sourced by the DCO-X circuitry, if the
transmit elastic buffer is enabled. Reference clock is XTAL1.
DCO-R cannot be used in this configuration.
Transmit data bypasses the buffer.
Transmit data bypasses the buffer.
FALC54 compatibility: Transmit data received on port XDI is
first written into the transmit jitter attenuator and then sent jitter
free on ports XL1/2 or XDOP/N or XOID.
For FALC-LH the same function even with a better support in
case of slips is also provided if bits are set to
SIC1.XBS1/0 = 10.
pins RL1/2 or RDIP/N or ROID is sent ’jitter free’ on ports XL1/
2 or XDOP/N or XOID. The dejittered clock is generated by the
DCO-X circuitry.
The ternary interface is selected. Multifunction ports RL1/2 and
XL1/2 become analog in/outputs.
The digital dual rail interface is selected. Received data is
latched on multifunction ports RDIP/RDIN while transmit data is
output on pins XDOP/XDON.
215
FALC-LH V1.3
E1 Registers
PEB 2255
2000-07