peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 251

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

RPF…
Interrupt Status Register 1 (Read)
All bits are reset when ISR1 is read.
If bit IPC.VIS is set, interrupt statuses in ISR1 may be flagged although they are masked
via register IMR1. However, these masked interrupt statuses neither generate a signal
on INT, nor are visible in register GIS.
LLBSC…
RDO…
Note: Whereas the bit RSIS.RDO in the frame status byte indicates whether an overflow
Data Sheet
ISR1
occurred when receiving the frame currently accessed in the RFIFO, the
ISR1.RDO interrupt status is generated as soon as an overflow occurs and does
not necessarily pertain to the frame currently accessed by the processor.
LLBSC
7
Receive Pool Full
32 bytes of a frame have arrived in the receive FIFO. The frame is not
yet completely received.
Depending on bit LCR1.EPRM the source of this interrupt status
changed:
LCR1.EPRM=0: This bit is set, if the LLB activate signal or the LLB
deactivate signal, respectively is detected over a period of 25 ms with
a bit error rate less than 1/100.
The LLBSC bit is also set, if the current detection status is left, i.e., if
the bit error rate exceeds 1/100.
The actual detection status can be read from the RSP.LLBAD and
RSP.LLBDD, respectively.
PRBS Status Change
LCR1.EPRM=1: With any change of state of the PRBS synchronizer
this bit is set. The current status of the PRBS synchronizer is
indicated in RSP.LLBAD.
This interrupt status indicates that the CPU did not respond fast
enough to an RPF or RME interrupt and that data in RFIFO has been
lost. Even when this interrupt status is generated, the frame continues
to be received when space in the RFIFO is available again.
Line Loop Back Status Change
Receive Data Overflow
RDO
ALLS
XDU
251
XMB
XLSC
FALC-LH V1.3
XPR
E1 Registers
0
PEB 2255
2000-07
(69)