peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 327

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Interrupt Status Register 1 (Read)
All bits are reset when ISR1 is read.
If bit IPC.VIS is set, interrupt statuses in ISR1 may be flagged although they are masked
via register IMR1. However, these masked interrupt statuses neither generate a signal
on INT, nor are visible in register GIS.
CASE…
RDO…
ALLS…
Data Sheet
ISR1
CASE
7
In ESF format this bit is set with the beginning of a transmitted
multiframe related to the internal transmitter timing.
In F12 format this bit is set with the beginning of a transmitted
multiframe, if bit FMR5.SRS = 0. If FMR5.SRS = 1, this bit is set at
every second multiframe begin.
In F72 format this interrupt occurs every 12/24 frames (FMR5.SRS =
0/1) to inform the user that new bit-robbing data has to be written to
XS1...6 registers (see
(T1/J1)" on page
This interrupt status indicates that the CPU did not respond fast
enough to an RPF or RME interrupt and that data in RFIFO has been
lost. Even when this interrupt status is generated, the frame continues
to be received when space in the RFIFO is available again.
Note:Whereas the bit RSIS.RDO in the frame status byte indicates
All Sent
This bit is set if the last bit of the current frame has been sent out
completely and XFIFO is empty.
Transmit CAS Register Empty
Receive Data Overflow
RDO
whether an overflow occurred when receiving the frame
currently accessed in the RFIFO, the ISR1.RDO interrupt
status is generated as soon as an overflow occurs and does
not necessarily pertain to the frame currently accessed by the
processor.
ALLS
146).
XDU
327
Table 36 "72-Frame Multiframe Structure
XMB
XLSC
FALC-LH V1.3
T1/J1 Registers
XPR
0
PEB 2255
2000-07
(69)