peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 234

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

LMFA…
Framer Receive Status Register 1 (Read)
TS16RA…
TS16LOS…
TS16AIS…
Data Sheet
FRS1
7
TS16RA
Loss of Multiframe Alignment
Not used in doubleframe format (FMR2.RFS1 = 0). In this case, LMFA
is set.
In CRC-multiframe mode (FMR2.RFS1 = 1), this bit is set
– if force resynchronization is initiated by setting bit FMR0.FRS, or
– if multiframe force resynchronization is initiated by setting bit
– if pulseframe alignment has been lost (FRS0.LFA).
It is reset if two CRC-multiframes have been received at an interval of
n
If bit FRS0.LMFA is cleared a loss of multiframe alignment recovery
interrupt status ISR2.MFAR is generated.
This bit contains the actual information of the received remote alarm
bit RS1.2 in time slot 16. Setting and resetting of this bit causes an
interrupt status change ISR3.RA16.
Receive Timeslot 16 Loss of Signal
This bit is set if the incoming TS16 data stream contains always zeros
for at least 16 contiguously received time slots. A one in a time slot 16
resets this bit.
The detection of the alarm indication signal in timeslot 16 is according
to ITU-T G.775.
This bit is set if the incoming TS16 contains less than 4 zeros in each
of two consecutive TS16 multiframe periods. This bit is cleared if two
consecutive received CAS multiframe periods contains more than 3
zeros or the multiframe pattern was found in each of them. This bit is
cleared if TS0 synchronization is lost.
Receive Timeslot 16 Remote Alarm
Receive Timeslot 16 Alarm Indication Signal
FMR1.MFCS, or
2 ms (n = 1, 2, 3…) without a framing error.
TS16LOS
TS16AIS TS16LFA
234
XLS
FALC-LH V1.3
XLO
E1 Registers
0
PEB 2255
2000-07
(4D)