peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 283

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Transmit Control 0 (Read/Write)
Value after RESET: 00
BRM…
MFBS…
SFRZ…
XCO2…XCO0… Transmit Clock Slot Offset
Data Sheet
XC0
BRM
7
A one in this bit marks the robbed bit positions on the system highway.
RSIGM marks the receive and XSIGM marks the transmit robbed bits.
For correct operation bit FMR1.SIGM must be set.
Enable pure Multiframe Begin Signals
Valid only if ESF or F72 format is selected.
If set, signals RMFB and XMFB indicate only the multiframe begin.
Additional pulses (every 12 frames) are disabled.
Select Freeze Output
0…
1…
Initial value loaded into the transmit bit counter at the trigger edge of
SCLKX when the synchronous pulse on port SYPX is active. Setting
of SIC1.SXSC enforces programming the offset values in the range
of 0 to 192 bits with XCO0 always cleared.
Enable Bit-Robbing Marker
MFBS
H
Signal RFSP is output on port RFSP/FREEZS
Freeze status signal is output on port RFSP/FREEZS
SFRZ
283
XCO2
XCO1
FALC-LH V1.3
T1/J1 Registers
XCO0
0
PEB 2255
2000-07
(20)