peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 143

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

• two or more erroneous framing bits within one ESF multiframe
• 4 incorrect (1 out of 6) consecutive multiframes independent of CRC6 errors.
There are four multiframe synchronization modes selectable via FMR2.MCSP and
FMR2.SSP.
• FMR2.MCSP/SSP = 00
• FMR2.MCSP/SSP = 01
• FMR2.MCSP/SSP = 10
• FMR2.MCSP/SSP = 11
Data Sheet
In the synchronous state, the setting of FMR0.FRS or FMR0.EXLS resets the
synchronizer and initiates a new frame search. The synchronous state is reached
again, if there is only one definite framing candidate. In the case of repeated apparent
simulated candidates, the synchronizer remains in the asynchronous state.
In asynchronous state, setting bit FMR0.FRS induces the synchronizer to lock onto
the next available framing candidate if there is one. At the same time the internal
framing pattern memory is cleared and other possible framing candidates are lost.
Synchronization is achieved when 3 consecutive multiframe pattern are correctly
found independent of the occurrence of CRC6 errors. If only one or two consecutive
multiframe pattern were detected the FALC
searching for a possible additionally available framing pattern. This procedure is
repeated until the framer has found three consecutive multiframe pattern in a row.
This mode has been added in order to be able to choose multiple framing pattern
candidates step by step. I.e. if in synchronous state the CRC error counter indicates
that the synchronization might have been based on an alias framing pattern, setting
of FMR0.FRS leads to synchronization on the next candidate available. However, only
the previously assumed candidate is discarded in the internal framing pattern
memory. The latter procedure can be repeated until the framer has locked on the right
pattern (no extensive CRC errors).
The synchronizer is completely reset and initiates a new frame search, if there is no
multiframing found. In this case bit FSR0.FSRF toggles.
Synchronization including automatic CRC6 checking
Synchronization is achieved when framing pattern are correctly found and the CRC6
checksum is received without an error. If the CRC6 check failed on the assumed
framing pattern the FALC
possible available framing pattern. This procedure is repeated until the framer has
locked on the right pattern. This automatic synchronization mode has been added in
order to reduce the microprocessor load.
®
-LH stays in the asynchronous state, searching for a
143
®
-LH stays in the asynchronous state,
Functional Description T1/J1
FALC-LH V1.3
PEB 2255
2000-07