peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 200

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

ECLB…
CLA4...0…
Transmit Service Word Pulseframe (Read/Write)
Value after RESET: 00
XSIS…
XTM…
Data Sheet
XSW
XSIS
7
0...
1...
CLA = 0…31 selects the channel.
During looped back the contents of the assigned outgoing channel on
ports XL1/XDOP/XOID and XL2/XDON is equal to the idle channel
code programmed at register IDLE.
Spare Bit For International Use
First bit of the service word. Only significant in doubleframe format. If
not used, this bit should be fixed to ‘1’. If one of the time slot 0
transparent modes is enabled (bit XSP.TT0, or TSWM.TSIS), bit
XSW.XSIS is ignored.
Transmit Transparent Mode
0…Ports SYPX/XMFS define the frame/multiframe begin on the
transmit system highway. The transmitter is usually synchronized on
this externally sourced frame boundary and generates the FAS bits
according to this framing. Any change of the transmit time slot
assignment or a transmit slip subsequently produces a change of the
FAS bit positions.
1… Disconnects the control of the transmit system interface from the
transmitter. The transmitter is now in a free running mode without any
possibility to update the multiframe position. The framing (FAS bits)
generated by the transmitter are not disturbed (in case of changing
the transmit time slot assignment or transmit slip) by the transmit
system highway unless register XC1 is written. Useful in loop-timed
applications. For correct operation the transmit elastic buffer (2
frames, SIC1.XBS1/0= 10) has to be enabled.
Enable Channel Loop Back
Channel Address For Loop Back
XTM
H
Disables the channel loop back.
Enables the channel loop back selected by this register.
XRA
XY0
200
XY1
XY2
XY3
FALC-LH V1.3
XY4
E1 Registers
0
PEB 2255
2000-07
(1E)