peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 178

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

8.3.10.1 Data Link Access in ESF/F72 Format (T1/J1)
The FALC
as follows:
• Sampling of DL bits is done on a multiframe basis and stored in the registers RDL1...3.
• If enabled by CCR1.EDLX/EITS=10, the DL-bit information is stored in the Receive
Data Sheet
A receive multiframe begin interrupt is provided to read the received data DL bits. The
contents of registers XDL1...3 is subsequently sent out on the transmit multiframe
basis if it is enabled via FMR1.EDL. A transmit multiframe begin interrupt requests for
writing new information to the DL-bit registers.
FIFO of the signaling controller. The DL-bits stored in the XFIFO are inserted into the
outgoing data stream. If CCR1.EDLX is cleared, a HDLC- or a transparent- frame can
be sent or received via the RFIFO/XFIFO.
®
-LH supports the DL-channel protocol using the ESF or F72 (SLC96) format
178
Signaling Controller Operating Modes
FALC-LH V1.3
PEB 2255
2000-07