peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 285

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

SICS…
CRCI…
XCRCI…
RDIS…
RCO2…RCO0… Receive Offset/Receive Frame Marker Offset
Data Sheet
0
Data in the second channel phase is tristated.
Data on pin XDI is sampled in the first channel phase only. Data in the
second channel phase is ignored.
1
phase. Data in the first channel phase is tristated.
Data on pin XDI is sampled in the second channel phase only. Data
in the first channel phase is ignored.
If set, all CRC bits of one outgoing extended multiframe are inverted
in case a CRC error is flagged for the previous received multiframe.
This function is logically ORed with RC0.XCRCI.
If set, the CRC bits in the outgoing data stream are inverted before
transmission. This function is logically ORed with RC0.CRCI.
Only applicable for dual rail mode (LIM1.DRS = 1).
0
1
Depending on bit SIC2.SRFSO this bit enables different functions:
Receive Clock-Slot Offset (SIC2.SRFSO = 0)
Initial value loaded into the receive bit counter at the trigger edge of
SCLKR when the synchronous pulse on port SYPR is active. Setting
of SIC1.SRSC enforces programming the offset values in a range of
0 to 192 bits with RCO0 always cleared.
Receive Frame Marker Offset (SIC2.SRFSO = 1)
Offset programming of the receive frame marker which is output on
port SYPR. The receive frame marker could be activated during any
bit position of the current frame.
Calculation of the value X of the “Receive Counter Offset” register
RC1/0 depends on the bit position BP which should be marked and
SCLKR: X = (2BP) mod 386, for SCLKR = 1.544 MHz
System Interface Channel Select
Automatic CRC6 Bit Inversion
Transmit CRC6 Bit Inversion
Receive Data Input Sense
Applicable only if bit FMR1.IMOD (4-MHz system interface) is
cleared.
Received data is output on port RDO in the first channel phase.
Inputs: RDIP, RDIN active low, input ROID is active high
Inputs: RDIP, RDIN active high, input ROID is active low
Received data is output on port RDO in the second channel
285
FALC-LH V1.3
T1/J1 Registers
PEB 2255
2000-07