peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 97

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

4.6
4.6.1
The FALC
bit sequences (PRBS). The generated PRBS pattern is transmitted optionally inverted or
not to the remote end via pins XL1/2 or XDOP/N. Generating and monitoring of PRBS
pattern is done according to ITU-T O. 151.
The PRBS monitor senses the PRBS pattern in the incoming data stream.
Synchronization is done on the inverted and non inverted PRBS pattern. The current
synchronization status is reported in status and interrupt status registers. Enabled by bit
LCR1.EPRM each PRBS bit error increments an error counter (CEC2). Synchronization
is reached within 400 ms with a probability of 99.9% and a bit error rate of 1/10. If an ’all
0’ or ’all 1’ signal is detected, synchronous state is indicated, too.
4.6.2
In the remote loopback mode the clock and data recovered from the line inputs RL1/2 or
RDIP/RDIN are routed back to the line outputs XL1/2 or XDOP/XDON via the analog or
digital transmitter. As in normal mode they are also processed by the synchronizer and
then sent to the system interface.The remote loopback mode is selected by setting the
respective control bits LIM1.RL+JATT. Received data may be looped with or without the
transmit jitter attenuator (FIFO = JATT).
Figure 27
Data Sheet
RL1
RL2
XL1
XL2
XCLK
®
Test Functions (E1)
Pseudo-Random Bit Sequence Generation and Monitor
Remote Loop
-LH has the ability to generate and monitor 2
Remote Loop (E1)
Clock +
Data
Recovery
MUX
MUX
RCLK
RCLK
DCO1/2
FIFO
97
Rec.
Framer
Trans.
Framer
15
-1 and 2
Functional Description E1
Elast.
Store
Elast.
Store
20
-1 pseudo-random
FALC-LH V1.3
ITS09750
PEB 2255
RDO
XDI
2000-07