peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 183

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

9.2
Transmit FIFO (Write)
Command Register (Write)
Value after RESET: 00
RMC…
RRES…
XREP…
Data Sheet
XFIFO
CMDR
RMC
XF7
Detailed Description of E1 Control Registers
7
7
Writing data to XFIFO can be done in 8-bit (byte) or 16-bit (word)
access. The LSB is transmitted first.
Up to 32 bytes/16 words of transmit data can be written to the XFIFO
following a XPR (or ALLS) interrupt.
Confirmation from CPU to FALC
block has been fetched following a RPF or RME interrupt, thus the
occupied space in the RFIFO can be released.
The receive line interface except the clock and data recovery unit
(DPLL), the DCR-R circuitry, the receive framer, the one second timer
and the receive signaling controller are reset. However the contents
of the control registers is not deleted. RRES has to be given every
time after a configuration change.
If XREP is set together with XTF (write 24
repeatedly transmits the contents of the XFIFO (1 … 32 bytes)
without HDLC framing fully transparently, i.e. without FLAG,CRC.
The cyclic transmission is stopped with a SRES command or by
resetting XREP.
Note: During cyclic transmission the XREP-bit has to be set with
Receive Message Complete
Receiver Reset
Transmission Repeat
RRES
H
every write operation to CMDR.
XREP
XRES
183
XHF
®
-LH that the current frame or data
XTF
H
to CMDR), the FALC
XME
FALC-LH V1.3
SRES
XF0
E1 Registers
0
0
PEB 2255
(00/01)
2000-07
(02)
®
-LH