peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 261

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

10.2
Transmit FIFO (Write)
Writing data to XFIFO can be done in 8-bit (byte) or 16-bit (word) access. The LSB is
transmitted first.
Up to 32 bytes/16 words of transmit data can be written to the XFIFO following an XPR
(or ALLS) interrupt.
Command Register (Write)
Value after RESET: 00
RMC…
RRES…
XREP…
Data Sheet
XFIFO
CMDR
RMC
XF7
Detailed Description of T1/J1 Control Registers
7
7
Confirmation from CPU to FALC
block has been fetched following an RPF or RME interrupt, thus the
occupied space in the RFIFO can be released.
The receive line interface except the clock and data recovery unit
(DPLL), the receive framer, the one second timer and the receive
signaling controller are reset. However the contents of the control
registers is not deleted. Receiver reset shall be done after every new
device initialization.
If XREP is set together with XTF (write 24H to CMDR), the FALC
repeatedly transmits the contents of the XFIFO (1 32 bytes) without
HDLC framing fully transparently, i.e. without FLAG,CRC.
The cyclic transmission is stopped with an SRES command or by
resetting XREP.
Note:During cyclic transmission the XREP-bit has to be set with every
Receive Message Complete
Receiver Reset
Transmission Repeat
RRES
H
write operation to CMDR.
XREP
XRES
261
XHF
®
-LH that the current frame or data
XTF
XME
FALC-LH V1.3
T1/J1 Registers
SRES
XF0
0
0
PEB 2255
(00/01)
2000-07
(02)
®
-LH