peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 47

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

3.3
3.3.1
The communication between the CPU and the FALC
accessible registers. The interface may be configured as Intel or Motorola type with a
selectable data bus width of 8 or 16 bits.
The CPU transfers data to/from the FALC
sets the operating modes, controls function sequences, and gets status information by
writing or reading control/status registers. All accesses can be done as byte or word
accesses if enabled. If 16-bit bus width is selected, access to lower/upper part of the data
bus is determined by address line A0 and signal BHE/BLE as shown in
Table
In
structure and interface type. The switching of ALE allows the FALC
connected to a multiplexed address/data bus.
3.3.1.1
Reading from or writing to the internal FIFOs (RFIFO and XFIFO) can be done using a
8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode.
Randomly mixed byte/word access to the FIFOs is allowed without any restrictions.
If byte access is used, high byte or low byte can be used as well. Any value written to
high or low byte is placed in the FIFO in sequential order.
Data Sheet
Table 8
7.
is shown how the ALE (address latch enable) line is used to control the bus
Functional Blocks
Microprocessor Interface
Mixed Byte/Word Access to the FIFOs
®
47
-LH (via 64 byte deep FIFOs per direction),
Functional Description E1/T1/J1
®
-LH is done via a set of directly
®
-LH to be directly
FALC-LH V1.3
Table 6
PEB 2255
2000-07
and